Transversal filters are known which incorporate multistage devices, each stage being arranged to calculate the product of two digital signals together with means for adding together products formed by different stages. Such devices are known which achieve multiplication by repeated addition of partial products. However difficulties arise in achieving satisfactory speed of operation particularly where the signals to be multiplied involve a large number of bits. Addition of a plurality of partial products to achieve multiplication involves resolution of carry signals which are generated at one bit position for carrying to a bit position of higher significance. For multibit numbers it is necessary to use very high speed adders if undesirable delays are to be avoided in resolving any carry signals through all bit positions of a product forming operation. Further delays may also be introduced by the operation of adding together the results of a plurality of multiplying operations if the addition is delayed until the product of each separate multiplication has been formed.
It is an object of the present invention to improve the speed of digital signal processing in which repeated addition is carried out to achieve multiplication together with addition of a plurality of results of multiplication.